An Automated Process for Compiling Data ow Graphs into Recon gurable Hardware

| We describe a system, developed as part of the Cameron project, which compiles programs written in a single-assignment subset of C called SA-C into data ow graphs, and then into VHDL. The primary application domain is image processing. The system consists of an optimizing compiler which produces data ow graphs, and a data ow graph to VHDL translator. The method used for the translation is described here, along with some results on an application. The objective is not to produce yet another design entry tool, but rather to shift the programming paradigm from HDLs to an algorithmic level, thereby extending the realm of hardware design to the application